19-5071; 12/09 DS2502-E48 48-bit node address chip 1 of 4 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . www.maxim-ic.com features ? factory programmed 48-bit node address chip with 768 bits user-programmable otp- eprom communicates with the economy of one signal plus ground ? provides valid mac-48/eui-48 ethernet address ? unique, factory lasere d and tested 64-bit registration number assures absolute traceability because no two parts are alike ? built-in multidrop controller ensures compatibility with other 1-wire ? products ? device is an ?add-only? memory where additional data can be programmed into eprom without disturbing existing data ? reduces control, address, data, power and programming signals to a single pin ? directly connects to a single port pin of a microprocessor and communicates at up to 16.3kbps ? presence detector acknowledges when reader first applies voltage ? low cost to-92 or tsoc surface mount packages ? reads over a wide voltage range of 2.8v to 6.0v from -40c to +85c; programs at 11.5v to 12.0v from -40c to + 50c pin configuration to-92 bottom view tsoc package top view ordering information part temp range pin- package DS2502-E48+ -40c to +85c 3 to-92 ds2502p-e48+ -40c to +85c 6 tsoc ds2502p-e48+t&r -40c to +85c 6 tsoc + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. 1-wire is a registered trademark of maxim integrated products, inc. description the DS2502-E48 is a variant of the ds2502 1024-bit ad d-only memory. it differs from the standard ds2502 in its custom rom family code 89h, and the uniqueware identifier 5e 7h in place of the upper 12 bits of the standard rom serializ ation field. otherwise, th e electrical and logical behavior is identical to that of the ds2502. for technical detail s please refer to the ds2502 data sheet.
DS2502-E48 2 of 4 the first 32 bytes of the DS2502-E48?s eprom memory contain a globally un ique 48-bit node address and are write-protected. the data structure follows the conventions of uniqueware devices using default data structure (figure 1). this fo rmat is also known as udp (univers al data packet) and is commonly used in 1-wire apis. therefore, if using one of those apis one can call a high level function to read and verify the inverted crc16. the udp is defined in application note 114, 1-wire file structure , and the apis can be found in the 1-wire software development kits . figure 1. node address chip data structure (unused) crc16 msb lsb company id value msb lsb extension id value msb lsb project id msb lsb length 19 bytes ffh 2 bytes 3 bytes constant 006035h 3 bytes serialization 4 bytes constant 00001129h 1 byte 0ah high address low address the data record starts with a length byte (0ah) and the 4-byte uniqueware project id 00001129h. the next 6 bytes contain the 48-bit node address which consists of an incr ementing 24-bit extension identifier and the ieee-assigned 24-bit company id value 006035h. an inverted 16-bit crc ends the data record. the remaining bytes of the 32-byte memory page remain unprogrammed. neither the 24-bit extension identifier nor the 24-bit company id are related to the 64-bit rom regi stration number. the rom registration number is used to provide a unique address to access the DS2502-E48 when multidropped on a 1-wire bus. example assume that a manufacturer?s company id value is 006035h and the 24-bit ex tension identifier is 67abcdh. the 48-bit node address value generated from these tw o numbers is 00603567abcdh, whose byte and bit representations ar e illustrated in figure 2. figure 2. sample node address value most significant byte least significant byte 00 60 35 67 ab cd hex 0000 0000 0110 0000 0011 0101 0110 0111 1010 1011 1100 1101 binary most significant bit least significant bit this information is stored in th e DS2502-E48 as 48-bit numbe r with the leas t significant byte at the lower address. including the length byte and the inverted crc, the complete set of data is shown in figure 3. figure 3. physical address and da ta mapping inside the device address 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 data 8d dd 00 60 35 67 ab cd 00 00 11 29 0a
DS2502-E48 3 of 4 the four bytes at memory addr esses 01h to 04h contain the uni queware project id 00001129h. the two bytes at addresses 0bh and 0ch ar e the inverted 16-bit crc over the length byte, project id and node address value. the least significant byte of the crc is stored at address 0bh. this crc is generated according to the standardized crc16 polynomial function x 16 + x 15 + x 2 + 1. for more details on generating crc values including exam ples in both hardware and soft ware, see application note 27, understanding and using cyclic redundancy checks with maxim ibutton products . the contents of the memory address range 0dh to 1fh is ffh. these cells cannot be altered since the whole memory page is write-pro tected. the memory range from 20h to 7fh, however, is user- programmable. it can be write-prote cted by programming the corresponding write-protect bit in the status memory of the DS2502-E48.
DS2502-E48 4 of 4 revision history revision date description pages changed changed the ordering information to lead free. 1 included an explanation of ?default data structure? above figure 1. 2 emphasized that the 16-bit crc is inverted. 2 deleted paragraph on how to set up a uniqueware project. 2 inserted actual crc value to figure 3. 2 reformatted figures 1 to 3. 2 12/09 corrected notation of hexadecimal numbers from h to h. 1, 2, 3
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